#ifndef HW_MEMMAP_H
#define HW_MEMMAP_H

/* memery map for peripheral */
#define ADCARESULT_BASE 0x01000000U
#define ADCBRESULT_BASE 0x01001000U
#define ADCCRESULT_BASE 0x01002000U
#define ADCDRESULT_BASE 0x01003000U
#define ADCERESULT_BASE 0x01008000U
#define ADCFRESULT_BASE 0x01009000U
#define ADCGRESULT_BASE 0x0100a000U
#define ADCHRESULT_BASE 0x0100b000U

#define DCSM_Z1OTP_BASE      0x01004000U
#define DCSMBANK0_Z1OTP_BASE 0x01004800U
#define DCSM_Z2OTP_BASE      0x01005000U
#define DCSMBANK0_Z2OTP_BASE 0x01005400U
#define DCSMCOMMON_BASE      0x01005800U

#define DMA_BASE     0x01006000U
#define DMA_CH1_BASE 0x01006100U
#define DMA_CH2_BASE 0x01006200U
#define DMA_CH3_BASE 0x01006300U
#define DMA_CH4_BASE 0x01006400U
#define DMA_CH5_BASE 0x01006500U
#define DMA_CH6_BASE 0x01006600U

#define PIECTRL_BASE        0x007F0100U
#define DEBUG_BASE          0x007F0200U
#define CPUTIMER0_BASE      0x007F0300U
#define CPUTIMER1_BASE      0x007F0320U
#define CPUTIMER2_BASE      0x007F0340U
#define CR_BASE             0x007F0400U
#define GR_BASE             0x007F0500U
#define MOB_BASE            0x007F0600U
#define EXP_BASE            0x007F0700U
#define WD_BASE             0x007F0800U
#define IPC_CPUXTOCPUX_BASE 0x007F0900U
#define IPC_CPU1_CLA1_BASE  0x007F0900U
#define IPC_CPU2_CLA2_BASE  0x007F0900U
#define IPC_CMD_BASE        0x007F0A00U
#define VCU_BASE            0x007F0B00U
#define TRACE_BUFFER_BASE   0x007F0C00U
#define WATCH_POINT_BASE    0x007F0D00U
#define ECC_BASE            0x007F0E00U
#define ERAD_GLOBAL_BASE    0x007F0F00U
#define ERAD_HWBP1_BASE     0x007F1000U
#define ERAD_HWBP2_BASE     0x007F1100U
#define ERAD_HWBP3_BASE     0x007F1200U
#define ERAD_HWBP4_BASE     0x007F1300U
#define ERAD_HWBP5_BASE     0x007F1400U
#define ERAD_HWBP6_BASE     0x007F1500U
#define ERAD_HWBP7_BASE     0x007F1600U
#define ERAD_HWBP8_BASE     0x007F1700U
#define ERAD_COUNTER1_BASE  0x007F1800U
#define ERAD_COUNTER2_BASE  0x007F1900U
#define ERAD_COUNTER3_BASE  0x007F1A00U
#define ERAD_COUNTER4_BASE  0x007F1B00U
#define CLA1_BASE           0x007F1C00U

#define EPWM1_BASE  0x01010000U
#define EPWM2_BASE  0x01011000U
#define EPWM3_BASE  0x01012000U
#define EPWM4_BASE  0x01013000U
#define EPWM5_BASE  0x01014000U
#define EPWM6_BASE  0x01015000U
#define EPWM7_BASE  0x01016000U
#define EPWM8_BASE  0x01017000U
#define EPWM9_BASE  0x01018000U
#define EPWM10_BASE 0x01019000U
#define EPWM11_BASE 0x0101A000U
#define EPWM12_BASE 0x0101B000U
#define EPWM13_BASE 0x0101C000U
#define EPWM14_BASE 0x0101D000U
#define EPWM15_BASE 0x0101E000U
#define EPWM16_BASE 0x0101F000U
#define EPWM17_BASE 0x01020000U
#define EPWM18_BASE 0x01021000U

#define EQEP1_BASE 0x01022000U
#define EQEP2_BASE 0x01023000U
#define EQEP3_BASE 0x01024000U
#define EQEP4_BASE 0x01025000U
#define EQEP5_BASE 0x01026000U
#define EQEP6_BASE 0x01027000U

#define ECAP1_BASE  0x01028000U
#define ECAP2_BASE  0x01029000U
#define ECAP3_BASE  0x0102A000U
#define ECAP4_BASE  0x0102B000U
#define ECAP5_BASE  0x0102C000U
#define HRCAP6_BASE 0x0102D000U
#define HRCAP7_BASE 0x0102E000U

#define HRPWMCAL1_BASE  0x0102E800U
#define HRPWMCAL2_BASE  0x0102E900U
#define HRPWMCAL3_BASE  0x0102EA00U
#define HHRPWMCAL1_BASE 0x0102EC00U
#define HHRPWMCAL2_BASE 0x0102ED00U
#define HHRPWMCAL3_BASE 0x0102EE00U

#define CMPSS1_BASE  0x0102F000U
#define CMPSS2_BASE  0x01030000U
#define CMPSS3_BASE  0x01031000U
#define CMPSS4_BASE  0x01032000U
#define CMPSS5_BASE  0x01033000U
#define CMPSS6_BASE  0x01034000U
#define CMPSS7_BASE  0x01035000U
#define CMPSS8_BASE  0x01036000U
#define CMPSS9_BASE  0x01037000U
#define CMPSS10_BASE 0x01038000U
#define CMPSS11_BASE 0x01039000U

#define DACA_BASE 0x0103A000U
#define DACB_BASE 0x0103B000U
#define DACC_BASE 0x0103C000U

#define SDFM1_BASE 0x0103D000U
#define SDFM2_BASE 0x0103E000U
#define SDFM3_BASE 0x0103F000U
#define SDFM4_BASE 0x01040000U

#define SPIA_BASE 0x01041000U
#define SPIB_BASE 0x01042000U
#define SPIC_BASE 0x01043000U
#define SPID_BASE 0x01044000U

#define DMA_MUX_BASE     0x01045000U
#define DMA_REQ_ACK_BASE 0x01046000U

#define FSITXA_BASE 0x01049000U
#define FSIRXA_BASE 0x0104A000U
#define FSITXB_BASE 0x0104B000U
#define FSIRXB_BASE 0x0104C000U
#define FSIRXC_BASE 0x0104D000U
#define FSIRXD_BASE 0x0104E000U

#define PMBUSA_BASE 0x0104F000U

#define ADCA_BASE 0x01050000U
#define ADCB_BASE 0x01051000U
#define ADCC_BASE 0x01052000U
#define ADCD_BASE 0x01053000U
#define ADCE_BASE 0x01054000U
#define ADCF_BASE 0x01055000U
#define ADCG_BASE 0x01056000U
#define ADCH_BASE 0x01057000U

#define EPWMXBARA_BASE     0x01060000U
#define EPWMXBARB_BASE     0x01061000U
#define INPUTXBAR_BASE     0x01062000U
#define XBAR_BASE          0x01063000U
#define CLBINPUTXBAR_BASE  0x01064000U
#define CLBXBAR_BASE       0x01065000U
#define OUTPUTXBAR_BASE    0x01066000U
#define CLBOUTPUTXBAR_BASE 0x01067000U
#define MINDBXBAR_BASE     0x01068000U
#define LCL_XBAR_BASE      0x01069000U

#define GPIODATA_BASE          0x0106A000U
#define GPIODATA_READ_BASE     0x0106A0A0U
#define GPIODATA_CLA_BASE      0x0106A100U
#define GPIODATA_CLA_READ_BASE 0x0106A1A0U
#define GPIOCTRL_BASE          0x0106B000U

#define DEVCFG_BASE  0x01070000U
#define SYNCSOC_BASE 0x01070130U
#define CLKCFG_BASE  0x01071000U
#define CPUSYS_BASE  0x01072000U

#define ANALOGSUBSYS_BASE 0x01073000U

#define EPG_BASE 0x01074000U

#define ADCSAFETYINTEVTAGG1_BASE 0x01075000U
#define ADCSAFETYINTEVTAGG2_BASE 0x01076000U
#define ADCSAFETYCHK1_BASE       0x01077000U
#define ADCSAFETYCHK2_BASE       0x01077100U
#define ADCSAFETYCHK3_BASE       0x01077200U
#define ADCSAFETYCHK4_BASE       0x01077300U
#define ADCSAFETYCHK5_BASE       0x01077400U
#define ADCSAFETYCHK6_BASE       0x01077500U
#define ADCSAFETYCHK7_BASE       0x01077600U
#define ADCSAFETYCHK8_BASE       0x01077700U

#define MEMCFG_BASE 0x01078000U

#define DCSM_Z1_BASE   0x01079000U
#define DCSM_Z2_BASE   0x0107A000U
#define DCSM_COMM_BASE 0x0107B000U

#define TRIM_BASE 0x0107C000U

#define NMI_BASE    0x0107D000U
#define SYSERR_BASE 0x0107E000U
#define XINT_BASE   0x0107F000U

#define CANA_BASE  0x01080000U
#define MCANB_BASE 0x01081000U
#define MCANA_BASE 0x01082000U

#define DCC0_BASE 0x01083000U
#define DCC1_BASE 0x01084000U
#define DCC2_BASE 0x01085000U

#define LINA_BASE 0x01086000U
#define LINB_BASE 0x01087000U

#define SCIA_BASE 0x01088000U
#define SCIB_BASE 0x01089000U

#define I2CA_BASE 0x0108A000U
#define I2CB_BASE 0x0108B000U

#define AESA_BASE    0x108F000U
#define AESA_SS_BASE 0x108FC00U

#define UPP_CTRL_BASE   0x0108C000U
#define UPP_TX_RAM_BASE 0x0108D000U
// #define UPP_RX_RAM_BASE 0x0108E000U

#define CLB1_BASE 0x01090000U
#define CLB2_BASE 0x01091000U
#define CLB3_BASE 0x01092000U
#define CLB4_BASE 0x01093000U
#define CLB5_BASE 0x01094000U
#define CLB6_BASE 0x01095000U

#define CLB1_LOGICCFG_BASE  0x01090000U
#define CLB1_LOGICCTRL_BASE 0x01090100U
#define CLB1_DATAEXCH_BASE  0x01090180U
#define CLB2_LOGICCFG_BASE  0x01091000U
#define CLB2_LOGICCTRL_BASE 0x01091100U
#define CLB2_DATAEXCH_BASE  0x01091180U
#define CLB3_LOGICCFG_BASE  0x01092000U
#define CLB3_LOGICCTRL_BASE 0x01092100U
#define CLB3_DATAEXCH_BASE  0x01092180U
#define CLB4_LOGICCFG_BASE  0x01093000U
#define CLB4_LOGICCTRL_BASE 0x01093100U
#define CLB4_DATAEXCH_BASE  0x01093180U
#define CLB5_LOGICCFG_BASE  0x01094000U
#define CLB5_LOGICCTRL_BASE 0x01094100U
#define CLB5_DATAEXCH_BASE  0x01094180U
#define CLB6_LOGICCFG_BASE  0x01095000U
#define CLB6_LOGICCTRL_BASE 0x01095100U
#define CLB6_DATAEXCH_BASE  0x01095180U

#define UARTA_BASE 0x01096000U
#define UARTB_BASE 0x01097000U

#define CPU1TOCPU2MSGRAM0_BASE 0x00200000U
#define CPU2TOCPU1MSGRAM0_BASE 0x00201000U
#define CPU1TOCLA1MSGRAM0_BASE 0x00202000U
#define CLA1TOCPU1MSGRAM0_BASE 0x00203000U
#define CPU2TOCLA2MSGRAM0_BASE 0x00204000U
#define CLA2TOCPU2MSGRAM0_BASE 0x00205000U

#define FLASH0CTRL_BASE 0x010A0000U

#define XINTF_BASE       0x20000000U
#define XINTF_ZONE0_BASE 0x20004000U
#define XINTF_ZONE6_BASE 0x20100000U
#define XINTF_ZONE7_BASE 0x20300000U

#define EMIF1CONFIG_BASE      0x0005F4C0U
#define ACCESSPROTECTION_BASE 0x0005F500U
#define MEMORYERROR_BASE      0x0005F540U
#define ROMWAITSTATE_BASE     0x0005F580U
#define ROMPREFETCH_BASE      0x0005F588U
#define TESTERROR_BASE        0x0005F590U

#define FLASH0DATA_BASE 0x30000000U
#define FLASH0OTP1_BASE 0x30200000U
#define FLASH0OTP2_BASE 0x30201000U

#define ECAT_BASE 0x40000000U
#define USB_BASE  0x41000000U

// 需要修改, 这里只是为了编译通过添加的定义
#define LFU_BASE      0x00007FE0U
#define SYSSTAT_BASE  0x0005D400U
#define PERIPHAC_BASE 0x0005D500U

#endif
